1. Field of the Invention
The present invention generally relates to a method of patterning vias in integrated circuit structures that avoids leaving residual organic material in the vias.
2. Description of the Related Art
Conventional methods for patterning vias often fill the via with a sacrificial organic material such as ARC (anti-reflective coating). However, many such conventional processes encounter the problem of being unable to completely remove the organic material from the via. This is an even more common problem with high aspect ratio vias that have a relatively narrow width compared to their length. The invention described below overcomes such conventional problems by avoiding using organic sacrificial materials within the vias.